Hardware Implmentation Approaches:
---------------------------------
1. Custom-built Motherboard card (for Intel Pentiums)
2. Altered Video Card (get a VideoCardKit and custom set it?)
3. Altered HiSpeed Network Switch (use the Packet or Cell cache
and disable the clear (assuming cells are used by first clearing
to all 1's, then ANDing in the new pattern) (WUGS Switch?)
R(A1..A4): (Raster order)
A1 A2 A3 A4
3 7 8 11
3 3 8 15
7 3 4 11
7 2 5 11
3 7 8 11
3 3 8 11
7 3 4 11
7 2 5 11
2 11 8 15
2 11 8 15
10 10 4 11
15 10 4 11
2 11 8 15
10 11 8 15
15 10 4 11
15 10 4 11
In 2-D space:
A1: A2: A3: A4:
3 3 7 7 7 3 3 2 8 8 4 5 11 15 11 11
3 3 7 7 7 3 3 2 8 8 4 5 11 11 11 11
2 2 10 15 11 11 10 10 8 8 4 4 15 15 11 11
2 10 15 15 11 11 10 10 8 8 4 4 15 15 11 11
R(A1..A4) (binary)
A1 A2 A3 A4
0011 0111 1000 1011
0011 0011 1000 1111
0111 0011 0100 1011
0111 0010 0101 1011
0011 0111 1000 1011
0011 0011 1000 1011
0111 0011 0100 1011
0111 0010 0101 1011
0010 1011 1000 1111
0010 1011 1000 1111
1010 1010 0100 1011
1111 1010 0100 1011
0010 1011 1000 1111
1010 1011 1000 1111
1111 1010 0100 1011
1111 1010 0100 1011
Since there are 16 rows (=4^2) and fanout=4
there will be 3 levels (Lev0=leaf, lev1, lev2=root)
lev2 ________________________________[]_________________________________
/ / \ \
/ / \ \
/ / \ \
/ / \ \
lev1 _____[0]_____ ______[1]_____ _____[2]_____ _____[3]_____
/ / \ \ / / \ \ / / \ \ / / \ \
/ / \ \ / / \ \ / / \ \ / / \ \
[0.0] [0.1] [0.2] [0.3] [1.0] [1.1] [1.2] [1.3] [2.0] [2.1] [2.2] [2.3] [3.0] [3.1] [3.2] [3.3]
^
`-lev0
First, we obviously need more compactification.
CompactCoding of level-0 4-bit patterns
-------------
The QID-counts for the top two levels will be positioned as follows:
[] (root)
[0] [1] [2] [3]
Right below that we will position a 1-digit-code for each level-0 4-bit pattern.
If the count is 1, show only the position of that single 1-bit (pos 0,1,2 or 3).
If the count is 2, use 4=01, 5=02, 6=03, 7=12, 8=13, 9=23
If the count is 3, show only the position of that single 0-bit +10 in hex (A,B,C,D)
(If the count is 0 or 4 there is no level-0)
The coding:
0: 1 0 1: 0 1 2: 0 0 3: 0 0
0 0 0 0 1 0 0 1
4: 1 1 5: 1 0 6: 1 0 7: 0 1 8: 0 1 9: 0 0
0 0 1 0 0 1 1 0 0 1 1 1
A: 0 1 B: 1 0 C: 1 1 D: 1 1
1 1 1 1 0 1 1 0
or graphically:
4--- 5| 6\ 7 / 8 | 9
| \ / | ---
When complementing:
For 2-bit patterns swap across 6.5: 6<->7 5<->8 4<->9
For -bit patterns add or subtract 10: 0<->A 1<->B 2<->C 3<->D
One could construct a lookup table for ANDing as well.
The bSQ files in 2-D spatial arrangement are:
A11 A12 A13 A14
0000 0011 1111 1111
0000 0011 1111 1111
0011 0001 1111 0001
0111 0011 1111 0011
A21 A22 A23 A24
0000 1000 1111 1110
0000 1000 1111 1110
1111 0000 1111 1100
1111 0000 1111 1100
A31 A32 A33 A34
1100 0011 0000 0001
1100 0011 0000 0001
1100 0011 0000 0000
1100 0011 0000 0000
A41 A42 A43 A44
1111 0100 1111 1111
1111 0000 1111 1111
1111 1100 1111 1111
1111 1100 1111 1111
BASIC CPtrees for attribute A1 and their complements:
P1,1 P1,2 P1,3 P1,4 P1,1' P1,2' P1,3' P1,4'
5 7 16 11 11 9 0 5
0 0 1 4 0 4 0 3 4 4 0 3 4 4 3 0 4 0 4 1 0 0 4 1
3 A A D 0 0
e.g., VALUE CPtrees for attribute A1 in 2-bit precision
P1(00) P1(01) P1(10) P1(11)
7 4 2 3
4 0 3 0 0 4 0 0 0 0 1 1 0 0 0 3
D 3 0 A
e.g., VALUE CPtrees for attribute A1 in 3-bit precision
P1(000) P1(010) P1(100) P1(110) P1(001) P1(011) P1(101) P1(111)
0 0 0 0 7 4 2 3
i 4 0 3 0 0 4 0 0 0 0 1 1 0 0 0 3
D 3 0 A
e.g., VALUE CPtrees for attribute A1 in 4-bit precision
P1(0000) P1(0100) P1(1000) P1(1100) P1(0010) P1(0110) P1(1010) P1(1110
0 0 0 0 3 0 2 0
0 0 3 0 0 0 1 1
D 3 0
P1(0001) P1(0101) P1(1001) P1(1101) P1(0011) P1(0111) P1(1011) P1(1111)
0 0 0 0 4 4 0 3
4 0 0 0 0 4 0 0 0 0 0 3
A
BASIC P1trees for attribute A1 and their complements:
P1,1 P1,2 P1,3 P1,4 P1,1' P1,2' P1,3' P1,4'
0 0 1 0 0 0 0 0
0 0 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 0 1 0
3 A A D 0 0
BASIC P1trees and their complements in Compact notation:
P1,1 P1,2 P1,3 P1,4 P1,1' P1,2' P1,3' P1,4'
0 0 1 0 0 0 0 0
0001 0100 1100 1100 1010 0010
3 A A D 0 0
P2,1 P2,2 P2,3 P2,4 P2,1' P2,2' P2,3' P2,4'
0 0 1 0 0 0 0 0
0011 0000 1010 1100 0111 1010
5 5 8 8
P3,1 P3,2 P3,3 P3,4 P3,1' P3,2' P3,3' P3,4'
0 0 0 0 0 0 1 0
1010 0101 0000 0101 1010 1011
8 5
P4,1 P4,2 P4,3 P4,4 P4,1' P4,2' P4,3' P4,4'
1 0 1 1 0 0 0 0
0010 0101
1 B
e.g., TUPLE CPtrees for (15,10,4,11) in 4-bit precision
P(15,10,4,11) = P1(1111) ^ P2(1010) ^ P3(0100) ^ P4(1011) = 3
0 0 0 3
A
You might want to check these yourselves (for practice).
(please report any errors - I'd guess there are some ;-)
The notes on classification in the 765 web site has this
dataset in full more detail (different coding scheme).
An interesting (maybe?) PredicatePtree is the
"HalfPure" or HPtree:
--------------------
Predicate is:
1-bit means Pure1 iff no children
0-bit means Pure0 iff no children
Cutting off any bottom level(s) results in another
HPtree of coarser granularity ("Rollup" operation)
In HPtrees multi-operand AND (n-operand AND) works:
if ANY operand is 0, the result = 0
if ALL operands are 1
and if <=1 has children, result = 1
and if >=1 has children, result = ?
then examine children
(result could be 1 or 0)
The HPtree of a complement is the complement tree
(just change every bit - note that this not usually the case).
HPtrees have the same leaves as Pure1 trees
(so UltraCompact notation can be used)
The Basic HPtrees for the above dataset are:
HP1,1 HP1,2 HP1,3 HP1,4 HP2,1 HP2,2 HP2,3 HP2,4
0 0 1 1 1 0 1 1
0001 0100 1100 0011 0000 1010
3 A A 5 5
HP3,1 HP3,2 HP3,3 HP3,4 HP4,1 HP4,2 HP4,3 HP4,4
0 0 0 0 1 0 1 1
1010 0101 0000 0010
8 1
HP1,15 = HP1,1111 = HP1,1^HP1,2^HP1,3^HP1,4
0
0000
A
vvvvvvvvvvvvvvvvvvvvvHardHatAreavvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
Stored by level (not by ptree) with ChildVectors:
I.
0011101100001011 Lev2
1101110111010100 CV2
0001010011000011000010101010010100000010 Lev1
0010000100010000100001000000000001001000 CV1
3AA5581 Lev0
II. Which comes from the following
(with "introns" or white space removed ;-)
HP-Tree ChildVector
bit1 bit2 bit3 bit4 bit1 bit2 bit3 bit4
A1 0 |0 |1 |1 1 |1 |0 |1
A2 1 |0 |1 |1 1 |1 |0 |1 Lev2
A3 0 |0 |0 |0 1 |1 |0 |1
A4 1 |0 |1 |1 0 |1 |0 |0
A1 0001|0100| |1100 0010|0001| |0001
A2 0011|0000| |1010 0000|1000| |0100 Lev1
A3 1010|0101| |0000 0000|0000| |0100
A4 |0010| | |1000| |
A1 3 | A| | A
A2 |5 | | 5 Lev0
A3 | | | 8 (coded patterns
A4 |1 | | of 16 bits)
These come from the Data Cubes below
I. is the same without structure (white space removed).
II. is slices along level.
HPtree
____________________
Lev0/ 3 / A/ / A/| ChildVectors
/____/____/____/____/ | ____________________
Lev1/0001/0100/ /1100/| | /0010/0001/ /0001/|
/____/____/____/____/ |/| /____/____/____/____/ |
Lev2/ / / / /| | | / / / / /| |
/____/____/____/____/ |/|/| /____/____/____/____/ |/|
A1 |0 |0 |1 |1 | | | | |1 |1 |0 |1 | | |
|____|____|____|____|/|/|/| |____|____|____|____|/|/|
A2 |1 |0 |1 |1 | | | / |1 |1 |0 |1 | | |
|____|____|____|____|/|/|/ |____|____|____|____|/|/|
A3 |0 |0 |0 |0 | | / |1 |1 |0 |1 | | /
|____|____|____|____|/|/ |____|____|____|____|/|/
A4 |1 |0 |1 |1 | / |0 |1 |0 |0 | /
|____|____|____|____|/ |____|____|____|____|/
bit1 bit2 bit3 bit4 bit1 bit2 bit3 bit4
Find VP1,15
HP1,15 = HP1,1111 = HP1,1^HP1,2^HP1,3^HP1,4
First we look at A1 stored by level:
HP-Tree(A1) ChildVector(A1)
bit1 bit2 bit3 bit4 bit1 bit2 bit3 bit4
0 |0 |1 |1 1 |1 |0 |1 Lev2
0001|0100| |1100 0010|0001| |0001 Lev1
3 | A| | A Lev0
0 |0 |1 |1 1 |1 |0 |1 Lev2Purity| | |1 | |
0001|0100| |1100 0010|0001| |0001 Lev1Purity|00 1|010 | |110 |
3 | A| | A Lev0Purity| 3 | A| | A|
-----------------------------
HP1,15 = HP1,1111 = HP1,1^HP1,2^HP1,3^HP1,4 |0 |
|000 |
| A|
Find TP(15,10,4,11)
Purity: A1 | A2 | A3 | A4
| | |
bit1 bit2 bit3 bit4|bit1 bit2 bit3 bit4|bit1 bit2 bit3 bit4|bit1 bit2 bit3 bit4
----|----|----|----|----|----|----|----|----|----|----|----|----|----|----|----
| |1 | | | |1 | | | |0 | |1 | |1 |1
00 1|010 | |110 |0011| 000| |1 10|1010|0101| |0 00| | 010| |
3 | A| | A| |5 | | 5 | | | | 8 | |1 | |
-------------------|-------------------|-------------------|-------------------
complement pattern: yes yes yes yes yes yes
Purity: A1 | A2 | A3 | A4
(after comp'ing) | | |
bit1 bit2 bit3 bit4|bit1 bit2 bit3 bit4|bit1 bit2 bit3 bit4|bit1 bit2 bit3 bit4
----|----|----|----|----|----|----|----|----|----|----|----|----|----|----|----
| |1 | | | |1 | | | |1 | |1 | |1 |1
00 1|010 | |110 |0011| 111| |0 01|0101|0101| |1 11| | 101| |
3 | A| | A| |8 | | 8 | | | | 5 | |B | |
-------------------|-------------------|-------------------|-------------------
HP(15,10,4,11) |0 |lev2
|000 |lev1
| A|lev0
UltraCompact "NibbleCode" coding:
Use the HexTable everywhere so the P1tree is:
222B
1249A377B7
3AA885B
How about a NibbleCodeTable (NCT) Lookup software implmentation?
- build a separate table for Complementing and ANDing (and ORing)
- BAL (Basic Asm Lang - for mainframe IBMs)
has table lookups at the instruction level!
(so that this becomes one instruction each just like AND)
How about a ByteCodeTable (BCT)?
How about a WordCodeTable (WCT)?
How about a MultiWordCodeTable, e.g., N-WordCodeTable (NWCT)?
^^^^^^^^^^^^^^^^^^^^HardHatArea^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^